Recently, a research team led by Assistant Professor Deng Hui from the Department of Mechanical and Energy Engineering at the Southern University of Science and Technology (SUSTech) published a paper entitled “An efficient approach for atomic-scale polishing of single-crystal silicon via plasma-based atom-selective etching”. It was published in the International Journal of Machine Tools and Manufacture, a top journal in the field of mechanical manufacturing, and was the front cover for the April 2021 edition (Figure 1). It proposes a new method for high-efficiency manufacturing of single-crystal silicon wafer with atomic-level surface based on plasma atom-selective etching was proposed.
Figure 1. The front cover of the April 2021 edition that presents this paper’s research
Single-crystal silicon is currently the most wildly used semiconductor material in the electronic industry. As the physical dimensions of integrated circuit (IC) chips are further reduced, the realization of more advanced technology nodes imposes stricter requirements on the quality of wafers. When the chip fabrication process will be carried out by a 3 nm or smaller technology node, atomic-level accuracy of wafer surface will be required by the lithography process.
Conventional mechanical polishing or chemical mechanical polishing (CMP) processes are based on plastic deformation to achieve material removal. Firstly, the mechanism of the above material removal process determines that it is hard to obtain a non-damaged surface. Additionally, the tool scale of the conventional process determines it is hard to obtain a regular surface atomic arrangement. Therefore, for the fabrication of high-performance IC chips, there is an urgent need to develop an ultraprecision polishing technique to polish Si wafers with perfect surface and subsurface qualities at the atomic level.
Based on the above requirements, Deng Hui’s research group proposed an ultra-precision polishing method based on the plasma-based atom-selective etching (PASE). The principle is shown in Figure 2. The rough surface of single-crystal silicon can be seen as composed of silicon atoms with different numbers of dangling bonds. In the PASE process, the silicon atom with three dangling bonds has the highest etching priority, followed by the silicon atom with two dangling bonds, and finally the silicon atom with one dangling bond. The difference in etching priority can be adjusted by plasma parameters.
Once the higher priority silicon atoms are removed, the sublayer silicon atoms will be exposed, causing the bonding state of the surface to change continuously. In Figure 2 (b), the process of polishing a rough area into a smooth surface by the PASE process is demonstrated. After multiple selections, the final smooth surface can be considered an equipotential surface, on which all the Si atoms have the same bonding state and are uniformly etched by plasma. Therefore, an atomic-level ultra-smooth surface can be obtained with the PASE process.
Figure 2. Schematic of the surface polishing mechanism of the proposed PASE process
Based on the above mechanism, the researchers optimized various process parameters such as plasma power and gas ratio. For a 2-inch single crystal silicon wafer (100), the material removal rate of the PASE process exceeds 0.7 μm/min. A ground Si (100) surface can be quickly leveled by PASE, with the Sa roughness being reduced from 195 nm to below 1.0 nm within five minutes, and the polished surface is proven to be crystallographically perfect by the observation under TEM (Figure 3). The PASE of (110) and (111) oriented Si wafers is also proven effective, demonstrating that PASE is a generic polishing approach for Si regardless of orientation.
Figure 3. The roughness evolution and polishing effect diagram of the PASE process
The PASE technology proposed by this research has no mechanical stress, so it effectively avoids damage such as shearing and extrusion caused by mechanical effects in the traditional polishing process. At the same time, this technology realizes an efficient polishing process without expensive polishing liquids and polishing pads that require harmless treatment.
Compared with the conventional CMP method, the PASE process shows great advantages. Since the PASE process can polish single crystal silicon wafers in all crystal orientations, it has great application potential in wafer processing in the electronic and electrical fields. In addition, this method is theoretically promising to achieve a large-scale smooth surface at the level of a single atomic layer, which provides new possibilities for cutting-edge fields such as the manufacture of quantum chips.
Zhidong Fang, a master’s student from the Department of Mechanical and Energy Engineering at SUSTech, and Zhang Yi, a doctoral student supported by the joint Ph.D. program between SUSTech and the University of East Anglia (UEA) in the UK, are the co-first authors of the paper. Assistant Professor Deng Hui is the corresponding author, and SUSTech is the correspondent unit of the paper. This project is supported by the National Natural Science Foundation of China (NSFC), the Science and Technology Innovation Committee of Shenzhen Municipality, and SUSTech.
Paper link: